1. Field of the Invention
The present invention relates to a vertical insulated gate field effect transistor.
2. Description of the Related Art
Miniaturization of semiconductor devices in a planar direction is required in order to increase the integration degree of a semiconductor integrated circuit (LSI) such as a memory using planar transistors formed on a semiconductor substrate and SoC (System on a chip). The miniaturization in the planar direction has a physical limitation due to limitation of lithography. Therefore, various types of vertical transistors which each include an active region vertically formed on a semiconductor substrate have been proposed as a method of increasing the integration degree of an LSI (refer to, for example, U.S. Pat. No. 5,308,778).
As a result of the increase in the integration degree of vertical transistors described in U.S. Pat. No. 5,308,778 and the like, the cross-sectional diameter of the vertical transistor is reduced, and accordingly a contact area between the transistor and the semiconductor substrate, for example, a source contact area is also reduced. Consequently, a problem of an increase in a contact resistance is raised.
The present invention provides a semiconductor device which allows the source contact resistance to be reduced by increasing the source contact area and a method of manufacturing the same.